The invention relates to a method for patterning a metal or metal silicide layer, and to a high-epsilon dielectric or ferroelectric capacitor in an integrated semiconductor circuit.
Conventional microelectronic memory elements (DRAMs) include a capacitor in which the information to be stored is stored in the form of a charge. Silicon oxide or silicon nitride layers having a dielectric constant of at most about 8 are usually used as a capacitor material. xe2x80x9cNovelxe2x80x9d capacitor materials (dielectrics or ferroelectrics) having significantly higher dielectric constants are required for reducing the size of the storage capacitor and also for fabricating non-volatile memories (FeRAMs).
A number of capacitor materials suitable for this purposexe2x80x94Pb(Zr, Ti)O3 [PZT], SrBi2Ta2O9 [SBT], SrTiO3 [ST] and (Ba, Sr)TiO3 [BST]xe2x80x94are specified in the article xe2x80x9cNeue Dielektrika {umlaut over (fur)} Gbit-Speicherchipsxe2x80x9d [New dielectrics for Gbit memory chips] by W. Hxc3x6nlein, Phys. Bl. 55 (1999), pages 51-53.
The use of such novel high-epsilon dielectrics/ferroelectrics gives rise to the difficulty that Si, the traditional electrode material, can no longer be used since it is not compatible with the oxidizing atmosphere required during the dielectric/ferroelectric deposition or heat treatment.
Appropriate electrode materials are primarily sufficiently inert metals and metal silicides. The patterning of such layers has, however, hitherto remained a largely unresolved problem since suitable etching gases for removing such layers are not known at the present time.
The article xe2x80x9cSilicid-Mikrostrukturen durch lokale Oxidationxe2x80x9d [Silicide microstructures by local oxidation] by S. Mantl, Phys. Bl. 51 (1995), pages 951-953, proposes patterning silicide layers by locally oxidizing the layer in order to fabricate buried interconnects and mesa structures made of metal silicide. On the other hand, a method for forming platinum silicide is disclosed e.g. in U.S. Pat. No. 5,401,677.
U.S. Patent No. U.S. Pat. No. 5,561,307 describes a ferroelectric capacitor in an integrated circuit, whose base electrode is formed from a Pt layer by means of an RIE (Reactive Ion Etching) process. However, the RIE process exhibits an unsatisfactory selectivity with respect to mask materials and Pt substrates and does not allow the fabrication of a base electrode with a well-defined edge profile.
Published European Patent Application EP 0 867 926 A1 describes a method for fabricating a capacitor electrode made of a platinum-group metal. In this method, a metal layer is applied to a substrate partly made of a:Si and partly made of tungsten nitride and is silicided in a subsequent heat treatment step. The silicided layer sections are removed, with the result that an electrode made of platinum remains above the tungsten nitride layer region.
Published German Patent Application DE 195 03 641 A1 describes a method for patterning a metal silicide layer in which an Si3N4 mask covering the metal silicide layer is used for predetermining the structure. The substrate is unpatterned Si.
It is accordingly an object of the invention to provide a high-epsilon dielectric or ferroelectric capacitor structure having a metal or metal silicide electrode, and a method for patterning a metal or metal silicide layer which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type. In particular, it is an object of the invention to provide a method for patterning a metal or metal silicide layer that enables, in a technologically simple manner, the fabrication of a high-epsilon dielectric or ferroelectric capacitor with a metal or metal silicide electrode in an integrated circuit. Furthermore, it is an object of the invention to fabricate a high-epsilon dielectric or ferroelectric capacitor structure having a metal or metal silicide electrode with a well-defined edge profile.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for patterning a metal layer, which includes steps of: providing a substrate; above the substrate, producing a patterning layer for structuring a structuring pattern; producing the patterning layer with a base layer zone and a sinking layer zone laterally surrounding the base layer zone, the base layer zone having a contour; depositing a metal layer onto the patterning layer; siliciding the metal layer, at least in a region of the metal layer lying on the sinking layer zone such that a metal silicide layer section is formed in the region; and performing an oxidation step such that the metal silicide layer section migrates into the sinking layer zone of the patterning layer and a metal region having a contour that is identical to the contour of the base layer zone remains on the base layer zone.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a method for patterning a metal silicide layer, which includes steps of: providing a substrate; above the substrate, producing a patterning layer for structuring a structuring pattern; producing the patterning layer with a base layer zone and a sinking layer zone laterally surrounding the base layer zone, the base layer zone having a contour; producing a metal silicide layer on the patterning layer; performing an oxidation step to oxidize the metal silicide layer at least in a section of the metal silicide layer in the sinking layer zone where the metal silicide layer migrates into the sinking layer zone; and during the oxidation step, a region of the metal silicide layer having a contour identical to the contour of the base layer zone remains on the base layer zone.
In general, the invention is based on burying, below an oxide, undesired regions of the unpatterned metal or metal silicide layer from which e.g. a base electrode for a capacitor is intended to be formed, instead of removing them in the hitherto customary manner by means of chemical or physical processes.
For this purpose, according to the invention, first a patterning layer with a pattern (prepatterned base layer zone) of the patterned metal layer to be formed is produced. Since the patterning layer can be realized from customary layer materials that are technologically simple to handle (Si, in particular polysilicon in the sinking layer zone; for example SiO2 in the base layer zone), this layer can be produced without difficulty using the customary planar-technology methods (layer deposition methods; layer patterning by lithography and etching techniques).
The prepatterned base layer zone preferably has a structure that is identical in relation to the metal layer (metal region) to be patterned. In other words, the base layer zone serves as a mask of the metal region to be formed, which is intended to be created by patterning the metal layer.
According to a first aspect of the invention, a metal layer is deposited above the patterning layer. The undesired regions of the metal layer which lie laterally outside the base layer zone are silicided and subsequently xe2x80x9csunkxe2x80x9d in the patterning layer by oxidation.
In this way, it is possible to form a patterned metal layer which includes metal to the greatest possible extent over the whole area and serves as an electrode, metallization layer or interconnect.
In particular, the patterned metal layer includes a patterned metal region which is essentially of the same structure in relation to the base layer zone, i.e. the outer contour of the base layer zone corresponds to the contour of the patterned metal region. In this case, in contrast to the lateral, sunk metal silicide layer section, the metal region produced is not altered in terms of its position, but can also be partially or completely silicided.
When a metal layer is deposited, it is also possible, however, to produce a patterned metal region which includes metal silicide over part of or the whole area. In this case, regions above the base layer zone (i.e. within the base electrode contour) are also silicided, but care then has to be taken to ensure that these silicided regions are not oxidized and thus likewise xe2x80x9csunkxe2x80x9d.
The electrical contact-connection of the patterned metal region to be produced is preferably formed by an electrical connection structure made of Si, in particular polysilicon, which is provided in the base layer zone. In this case, between the connection structure and the metal layer, an electrically conductive barrier layer is expediently deposited in order to afford protection against siliciding of the metal layer by the connection structure and also in order to afford protection of the connection structure against oxidation. This makes it possible, even when an Si connection structure is provided, to produce a metal region including metal over the whole area, e.g. in the form of a base electrode. Furthermore, the patterned metal region can also subsequently be contact-connected by, for example, a contact structure introduced in an insulation layer covering the metal region.
Preferably, on the deposited metal layer in the region above the base layer zone and at least where siliciding of the metal layer is later provided, an oxidation mask is produced in order to afford protection against oxidation of such silicided metal layer regions. This reliably precludes oxidation and xe2x80x9csinkingxe2x80x9d of silicided metal regions within the base electrode contour.
The sinking layer zone of the patterning layer is preferably made at least twice as thick as the metal layer. The sinking layer zone then has a depth large enough to ensure that the electrical and mechanical contact between the positionally fixed metal region above the base layer zone and the adjacent, lowered metal silicide layer section reliably breaks off.
According to a second aspect of the invention, a metal silicide layer is produced on the patterning layer.
On account of the siliciding that is already prescribed in this case, all that is required for the patterning of the metal silicide layer is oxidation of the undesired outer layer regions. A metal silicide region (e.g. base electrode of a capacitor) is formed which consists of metal silicide to the greatest possible extent over the whole area.
Since, in this case, in contrast to the first aspect of the invention, siliciding of a metal layer with a corresponding increase in the thickness thereof does not take place, it suffices for the sinking layer zone of the patterning layer to be thicker than the metal silicide layer. In particular, it may be about twice as thick as the metal silicide layer.
In accordance with an added feature of the invention, in either embodiment or aspect of the invention, an oxide layer formed during the oxidation in the sinking layer zone above the sunk metal silicide layer section is removed at least in a sidewall region of the metal or metal silicide region. This makes it possible also to utilize the uncovered sidewall region for construction e.g. of a capacitor. As a result, the effective area (i.e. the area which can be brought into contact with the high-epsilon dielectric or ferroelectric) of the base electrode and thus the capacitance of the capacitor can be increased considerably, if appropriate. Assuming an adequate layer thickness of the metal or metal silicide layer, it is possible to produce capacitors whose vertical base electrical area exceeds the horizontal base electrode area.
The abovementioned utilization of the vertical dimension, the positionally accurate and contour-defined transfer (made possible by the invention) of the zone structure of the patterning layer to the metal or metal silicide, and the capacitance-increasing effect brought about by using a high-epsilon dielectric or ferroelectric contribute to a significant reduction in the space requirement of the capacitor in the integrated circuit. Consequently, it is possible to obtain higher integration densities of memory elements, for example.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for patterning a metal or metal silicide layer, and a capacitor fabricated by this method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.